Task I have to do before release:

  • pySoC IP/Components management
  • System on Chip project management
  • System on Chip project compilation
  • VHDL testbench generation
  • Xilinx project generation
  • Altera project generation
  • Test System on Chip project on target board
  • Test, test, test
  • Create release candidate/Beta version ?!?


Thinks to do asap

  • More IPs !!!
  • VHDL coding rules (web site)
  • Python coding rules (web site)
  • Generate exception for each error detected
  • Add VHDL / Python pointers and documentation
  • Give real life examples
  • Add more flexibility (global project settings)
  • Open development process to other people
  • Define targets
  • Define GUI
  • Complete/update documentation
  • Buy APF27 and test it with pySoC winking smiley
  • Add timing informations and simulation results
  • Add interrupt interfaces support