To create pySoc, I used following tools:
- PsPad my preferred Windows text editor
- Eclipse the well known multi-purpose IDE with fllowing plugins:
- PyDev for Python project management
- VEditor provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
- subversive a SVN plugin for Eclipse
- Altera Quartus II WebEdition, the Altera FGPA/CPLD design tools
- Altera ModelSim WebEdition for VHDL simulation and validation.
- Xilinx ISE the Xilinx FPGA/CPLD design tools
Projects and web site with interesting tools/features:
- ZamiaCAD a modular and extensible platform for advanced hardware design, analysis, and research (based on eclipse).